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class="dropdown-item"><!----> <a href="/pages/ca4cfb/" class="nav-link">Vue3进阶</a></li><li class="dropdown-item"><!----> <a href="/pages/50e8d3/" class="nav-link">黑马Vue3</a></li></ul></div></div><div class="nav-item"><div class="dropdown-wrapper"><button type="button" aria-label="MFC" class="dropdown-title"><!----> <span class="title" style="display:;">MFC</span> <span class="arrow right"></span></button> <ul class="nav-dropdown" style="display:none;"><li class="dropdown-item"><!----> <a href="/pages/a4b108/" class="nav-link">MFC编程随记</a></li><li class="dropdown-item"><!----> <a href="/pages/41acbd/" class="nav-link">MFC实现ini配置文件的读取</a></li><li class="dropdown-item"><!----> <a href="/pages/951a7a/" class="nav-link">MFC实现点击列表头排序</a></li><li class="dropdown-item"><!----> <a href="/pages/a8598f/" class="nav-link">贴图法美化Button按钮</a></li><li class="dropdown-item"><!----> <a href="/pages/054516/" class="nav-link">MFC使用细节</a></li></ul></div></div><div class="nav-item"><div class="dropdown-wrapper"><button type="button" aria-label="闪存" class="dropdown-title"><!----> <span class="title" style="display:;">闪存</span> <span class="arrow right"></span></button> <ul class="nav-dropdown" style="display:none;"><li class="dropdown-item"><!----> <a href="/pages/b925b8/" class="nav-link">如何高效阅读嵌入式项目代码</a></li><li class="dropdown-item"><!----> <a href="/pages/28ec23/" class="nav-link">NAND Flash</a></li><li class="dropdown-item"><!----> <a href="/pages/62bf40/" class="nav-link">ARM 处理器</a></li><li class="dropdown-item"><!----> <a href="/pages/1a9374/" class="nav-link">嵌入式基础知识-存储器</a></li><li class="dropdown-item"><!----> <a href="/pages/aac5e3/" class="nav-link">闪存存储和制造技术概述</a></li><li class="dropdown-item"><!----> <a href="/pages/8f6056/" class="nav-link">芯片IO驱动力</a></li><li class="dropdown-item"><!----> <a href="/pages/d146b8/" class="nav-link">主流先进封装技术介绍</a></li><li class="dropdown-item"><!----> <a href="/pages/16f0ba/" class="nav-link">NAND Flash基础</a></li><li class="dropdown-item"><!----> <a href="/pages/90d8d0/" class="nav-link">基于PA算法的FTL引导</a></li><li class="dropdown-item"><!----> <a href="/pages/eb672b/" class="nav-link">SD逻辑擦除和物理擦除</a></li><li class="dropdown-item"><!----> <a href="/pages/747121/" class="nav-link">NAND Flash的SDR、ONFI、DDR接口</a></li><li class="dropdown-item"><!----> <a href="/pages/1eb351/" class="nav-link">【详解】Nand Flash必看知识</a></li><li class="dropdown-item"><!----> <a href="/pages/d2512a/" class="nav-link">【两万字详解】Nand Flash必看知识</a></li></ul></div></div><div class="nav-item"><div class="dropdown-wrapper"><button type="button" aria-label="面经" class="dropdown-title"><!----> <span class="title" style="display:;">面经</span> <span class="arrow right"></span></button> <ul class="nav-dropdown" style="display:none;"><li class="dropdown-item"><!----> <a href="/pages/d69946/" class="nav-link">虎牙C++技术面经</a></li><li class="dropdown-item"><!----> <a href="/pages/29251d/" class="nav-link">金山一面复习</a></li><li class="dropdown-item"><!----> <a href="/pages/c7c01f/" class="nav-link">完美世界秋招 C++ 游戏开发面经(Cpp部分)</a></li></ul></div></div><div class="nav-item"><div class="dropdown-wrapper"><button type="button" aria-label="其它" class="dropdown-title"><!----> <span class="title" style="display:;">其它</span> <span class="arrow right"></span></button> <ul class="nav-dropdown" style="display:none;"><li class="dropdown-item"><!----> <a href="/pages/fa256e/" class="nav-link">博客搭建</a></li><li class="dropdown-item"><!----> <a href="/pages/335531/" class="nav-link">网站收藏箱</a></li></ul></div></div> <!----></nav>  <ul class="sidebar-links"><li><section class="sidebar-group collapsable depth-0"><p class="sidebar-heading"><span>电子嵌入式通信协议</span> <span class="arrow right"></span></p> <!----></section></li><li><section class="sidebar-group collapsable depth-0"><p class="sidebar-heading open"><span>深入浅出SSD</span> <span class="arrow down"></span></p> <ul class="sidebar-links sidebar-group-items"><li><a href="/pages/4c6bf3/" class="sidebar-link">第1章 SSD综述</a></li><li><a href="/pages/5f66ac/" aria-current="page" class="active sidebar-link">第2章 SSD主控和全闪存阵列</a><ul class="sidebar-sub-headers"><li class="sidebar-sub-header level2"><a href="/pages/5f66ac/#_2-1-ssd-系统架构" class="sidebar-link">2.1 SSD 系统架构</a><ul class="sidebar-sub-headers"><li class="sidebar-sub-header level3"><a href="/pages/5f66ac/#_2-1-1-前端" class="sidebar-link">2.1.1 前端</a></li><li class="sidebar-sub-header level3"><a href="/pages/5f66ac/#_2-1-2-主控-cpu" class="sidebar-link">2.1.2 主控 CPU</a></li><li class="sidebar-sub-header level3"><a href="/pages/5f66ac/#_2-1-3-后端" class="sidebar-link">2.1.3 后端</a></li></ul></li><li class="sidebar-sub-header level2"><a href="/pages/5f66ac/#_2-2-全闪存阵列-afa" class="sidebar-link">2.2 全闪存阵列 AFA</a></li></ul></li><li><a href="/pages/4f49cc/" class="sidebar-link">第3章 SSD存储介质：闪存</a></li><li><a href="/pages/9a554c/" class="sidebar-link">第4章 SSD 主控</a></li><li><a href="/pages/e3fd38/" class="sidebar-link">第6章 FTL 综述</a></li><li><a href="/pages/b2dae7/" class="sidebar-link">第9章 ECC 原理</a></li></ul></section></li><li><section class="sidebar-group collapsable depth-0"><p class="sidebar-heading"><span>文件系统</span> <span class="arrow right"></span></p> <!----></section></li><li><section class="sidebar-group collapsable depth-0"><p class="sidebar-heading"><span>汇编语言</span> <span class="arrow right"></span></p> <!----></section></li><li><section class="sidebar-group collapsable depth-0"><p class="sidebar-heading"><span>STM32</span> <span class="arrow right"></span></p> <!----></section></li></ul> </aside> <div><main class="page"><div class="theme-vdoing-wrapper "><div class="articleInfo-wrap" data-v-06225672><div class="articleInfo" data-v-06225672><ul class="breadcrumbs" data-v-06225672><li data-v-06225672><a href="/" title="首页" class="iconfont icon-home router-link-active" data-v-06225672></a></li> <li data-v-06225672><span data-v-06225672>嵌入式软件开发</span></li><li data-v-06225672><span data-v-06225672>深入浅出SSD</span></li></ul> <div class="info" data-v-06225672><div title="作者" class="author iconfont icon-touxiang" data-v-06225672><a href="javascript:;" data-v-06225672>霜晨月</a></div> <div title="创建时间" class="date iconfont icon-riqi" data-v-06225672><a href="javascript:;" data-v-06225672>2024-06-03</a></div> <!----></div></div></div> <!----> <div class="content-wrapper"><div class="right-menu-wrapper"><div class="right-menu-margin"><div class="right-menu-title">目录</div> <div class="right-menu-content"></div></div></div> <h1><img src="">第2章 SSD主控和全闪存阵列<!----></h1> <!----> <div class="theme-vdoing-content content__default"><h1 id="第2章-ssd-主控和全闪存阵列"><a href="#第2章-ssd-主控和全闪存阵列" class="header-anchor">#</a> 第2章　SSD 主控和全闪存阵列</h1> <blockquote><p>SSD 主要由两大模块构成——主控和闪存介质。其实除了上述两大模块外，可选的还有缓存单元。</p> <p>主控是 SSD 的大脑，承担着指挥、运算和协调的作用：</p> <ol><li>一是实现标准主机接口与主机通信；</li> <li>二是实现与闪存的通信；</li> <li>三是运行 SSD 内部 FTL 算法。</li></ol> <p>可以说，一款主控芯片的好坏直接决定了 SSD 的性能、寿命和可靠性。</p></blockquote> <h2 id="_2-1-ssd-系统架构"><a href="#_2-1-ssd-系统架构" class="header-anchor">#</a> 2.1 SSD 系统架构</h2> <p>SSD 作为数据存储设备，是一种典型的（System on Chip）单机系统，有主控 CPU、RAM、操作加速器、总线、数据编码译码等模块。</p> <ul><li>操作对象：协议、数据命令、介质</li> <li>操作目的：写入和读取用户数据</li></ul> <p><strong>SSD 系统架构的概略图（见下图 2-1）</strong></p> <p>这款主控采用 ARM CPU，主要分为前端和后端两大部分。</p> <ul><li>前端（Host Interface Controller，主机接口控制器）： 跟主机打交道，接口可以是 SATA、PCIe、SAS 等。</li> <li>后端（Flash Controller，闪存控制器）： 跟闪存打交道并完成数据编解码和 ECC。</li> <li>除此之外还有缓冲（Buffer）、DRAM。</li> <li>模块之间通过AXI高速和APB低速总线互联互通，完成信息和数据的通信。</li></ul> <p>在此基础之上，由 SSD 固件开发者构筑固件（Firmware）统一完成 SSD 产品所需要的功能，调度各个硬件模块，完成数据从主机端到闪存端的写入和读取。</p> <p><img alt="2-1" data-src="https://cdn.jsdelivr.net/gh/xiaose-code/picx-images-hosting@master/jianrong/image.9nzm9vplgi.webp" loading="lazy" class="lazy"></p> <h3 id="_2-1-1-前端"><a href="#_2-1-1-前端" class="header-anchor">#</a> 2.1.1 前端</h3> <p>主机接口：与主机进行通信（数据交互）的标准协议接口，当前主要代表为 SATA、SAS 和 PCIe 等。表2-1所示是三者的接口速率。</p> <p>表 2-1 SATA、SAS、PCIe 接口速率</p> <table><thead><tr><th style="text-align:center;">接口</th> <th style="text-align:center;">速率（Gbps）</th></tr></thead> <tbody><tr><td style="text-align:center;">SATA</td> <td style="text-align:center;">6/3/1.5</td></tr> <tr><td style="text-align:center;">SAS</td> <td style="text-align:center;">12/6</td></tr> <tr><td style="text-align:center;">PCIe</td> <td style="text-align:center;">通道数 × 8（PCIe3.0）</td></tr></tbody></table> <ul><li>SATA（Serial Advanced Technology Attachment（串行高级技术附件））： 是一种基于行业标准的串行硬件驱动器接口，是由 Intel、IBM、Dell、APT、Maxtor 和 Seagate 公司共同提出的硬盘接口规范（见下图2-2）。</li></ul> <p><img alt="图2-2" data-src="https://cdn.jsdelivr.net/gh/xiaose-code/picx-images-hosting@master/jianrong/image.1ov9etj0ja.webp" loading="lazy" class="lazy"></p> <hr> <p>SAS（Serial Attached SCSI）： 即串行连接 SCSI，是新一代的 SCSI 技术，和现在流行的 Serial ATA（SATA）硬盘相同，都是采用串行技术以获得更高的传输速度，并通过缩短连接线改善内部空间等（见下图2-3）。</p> <ul><li><p>SAS 是并行 SCSI 接口之后开发出的全新接口，此接口的设计是为了改善存储系统的效能、可用性和扩充性，并且提供与 SATA 硬盘的兼容性。SAS 的接口技术可以向下兼容 SATA。</p></li> <li><p>具体来说，二者的兼容性主要体现在物理层和协议层。</p> <ul><li>在物理层，SAS 接口和 SATA 接口完全兼容，SATA 硬盘可以直接用在 SAS 的环境中；从接口标准上而言，SATA 是 SAS 的一个子标准，因此 SAS 控制器可以直接操控 SATA 硬盘，但是 SAS 却不能直接用在 SATA 的环境中，因为 SATA 控制器并不能对 SAS 硬盘进行控制。</li> <li>在协议层，SAS 由3种类型的协议组成，根据连接设备的不同使用相应的协议进行数据传输。
<ul><li>其中串行 SCSI 协议（SSP）用于传输 SCSI 命令；</li> <li>SCSI 管理协议（SMP）用于对连接设备的维护和管理；</li> <li>SATA 通道协议（STP）用于 SAS 和 SATA 之间数据的传输。</li></ul></li></ul></li></ul> <p><img alt="图2-3" data-src="https://cdn.jsdelivr.net/gh/xiaose-code/picx-images-hosting@master/jianrong/image.b8qasadb8.webp" loading="lazy" class="lazy"></p> <hr> <p>PCIe（Peripheral Component Interconnect Express）： 是一种高速串行计算机扩展总线标准，它原来的名称为3GIO。PCIe 属于高速串行点对点多通道高带宽传输，所连接的设备分配独享通道带宽，不共享总线带宽，主要支持主动电源管理、错误报告、端对端的可靠性传输、热插拔以及服务质量（QoS，Quality of Service）等功能。PCI Express 也有多种规格，从 PCI Express 1X 到 PCI Express 32X，意思就是1个通道到32个通道，能满足将来一段时间内出现的低速设备和高速设备的需求。PCI-Express 最新的接口是PCIe 4.0接口。</p> <p><strong>主要优势：</strong></p> <ul><li>数据传输速率高，目前最高的4.0版本可达到2GB/s（单向单通道速率）</li> <li>发展潜力大</li></ul> <p>图 2-4　PCIe 接口式插卡（AIC）</p> <p><img alt="图2-4" data-src="https://cdn.jsdelivr.net/gh/xiaose-code/picx-images-hosting@master/jianrong/image.9kg0c6j6hi.webp" loading="lazy" class="lazy"></p> <p>图 2-5　U.2 接口</p> <p><img alt="图2-5" data-src="https://cdn.jsdelivr.net/gh/xiaose-code/picx-images-hosting@master/jianrong/image.syrzdo8yr.webp" loading="lazy" class="lazy"></p> <p>前端是负责主机和 SSD 设备通信的接口，命令和数据传输通过前端总线流向或流出 SSD 设备。从硬件模块上来看，前端有 SATA/SAS/PCIe PHY 层，俗称物理层，接收串行比特数据流，转化成数字信号给前端后续模块处理。这些模块处理 NVMe/SATA/SAS 命令，它们接收并处理一条条命令和数据信息，涉及数据搬移会使用到 DMA。一般命令信息会排队放到队列中，数据会放到 SRAM 快速介质中。如果涉及加密和压缩功能，前端会有相应的硬件模块来做处理，若软件无法应对压缩和加密的快速需求，则会成为性能的瓶颈。</p> <p>从协议角度，以一条 SATA Write FPDMA 命令为例对上述内容进行说明。</p> <p>从主机端文件系统发出一条写命令请求，该请求到主板南桥 AHCI 寄存器后，AHCI 寄存器执行请求，即进行写操作，忽略文件系统到 AHCI 路径的操作细节，从 SSD 前端总线上看会发出如下的写交互操作（见图2-6）：</p> <p><img alt="图2-6" data-src="https://cdn.jsdelivr.net/gh/xiaose-code/picx-images-hosting@master/jianrong/image.3go89qm7id.webp" loading="lazy" class="lazy"></p> <ol><li>步骤1：主机在总线上发出 Write FPDMA 命令 FIS（Frame Information Structure，帧信息结构，是 SATA 为了实现异步传输数据块而使用的封包）。</li> <li>步骤2：SSD 收到命令后，判断自己内部写缓存（Write Buffer）是否有空间去接收新的数据。如果有，则发出 DMA Setup FIS 到主机端；否则什么也不发，主机端处于等待状态（这叫流控：数据流量控制）。</li> <li>步骤3：主机端收到 DMA Setup FIS 后，发送不大于 8KB 数据的 Data FIS 给设备。</li> <li>步骤4：重复步骤2和步骤3直到数据全部发送完毕。</li> <li>步骤5：设备（SSD）发送一个状态 Status FIS 给主机，表示从协议层面这条写命令完成全部操作。当然 Status 可以是一个 good status 或者一个 bad/error status，表示这条 Write FPDMA 命令操作正常或者异常完成。</li></ol> <h3 id="_2-1-2-主控-cpu"><a href="#_2-1-2-主控-cpu" class="header-anchor">#</a> 2.1.2 主控 CPU</h3> <p>SSD 控制器 SoC 模块一般由一颗或多颗 CPU 核组成，同时片上有 I-RAM、D-RAM、PLL、IO、UART、高低速总线等外围电路模块。CPU 负责运算、系统调度，IO 完成必要的输入输出，总线连接前后端模块。</p> <ul><li>固件运行在 CPU 核上</li> <li>I-RAM： 代码存储区</li> <li>D-RAM： 数据存储区</li> <li>多核CPU，软件可以是对称多处理（SMP）和非对称多处理（AMP）
<ul><li>对称多处理（SMP）： 共享 OS 和同一份执行代码，共享一份 I-RAM 和 D-RAM，资源共享；</li> <li>非对称多处理（AMP）： 多核分别执行不同代码，每核对应一份 I-RAM 和 D-RAM，每核独立运行，没有内存抢占导致代码速度执行变慢的问题。</li></ul></li></ul> <blockquote><p>当 SSD 的 CPU 要求计算能力更高时，除增加核数和单核 CPU 频率外，AMP 的设计方式更加适应计算和任务独立的要求，消除了代码和数据资源抢占导致执行速度过慢的问题。</p></blockquote> <p>SSD 的 CPU 外围模块包括 UART、GPIO、JTAG，这些都是程序必不可少的调试端口，另外还有定时器模块 Timer 及其他内部模块，比如 DMA、温度传感器、Power regulator 模块等。</p> <h3 id="_2-1-3-后端"><a href="#_2-1-3-后端" class="header-anchor">#</a> 2.1.3 后端</h3> <p>后端两大模块分别为 ECC 模块和闪存控制器（见图2-7）。</p> <p><img alt="图2-7" data-src="https://cdn.jsdelivr.net/gh/xiaose-code/picx-images-hosting@master/jianrong/image.45hhtrmugl.webp" loading="lazy" class="lazy"></p> <p>ECC 模块是数据编解码单元，由于闪存存储天生存在误码率，为了数据的正确性，在数据写入操作时应给原数据加入 ECC校验保护，这是一个编码过程。读取数据时，同样需要通过解码来检错和纠错，如果错误的比特数超过 ECC 纠错能力，数据会以“不可纠错”的形式上传给主机。这里的 ECC 编码和解码的过程就是由 ECC 模块单元来完成的。SSD 内的 ECC算法主要有 BCH 和 LDPC，其中 LDPC 正逐渐成为主流。</p> <p>闪存控制器使用符合闪存 ONFI、Toggle 标准的闪存命令，负责管理数据从缓存到闪存的读取和写入。</p> <blockquote><p>闪存控制器如何和闪存连接和通信？</p></blockquote> <p>从单个闪存角度看，一个 Die/LUN 是一个闪存命令执行的基本单元，闪存控制器和闪存连接引脚按照如下操作（见图2-8）：</p> <p><img alt="图2-8" data-src="https://cdn.jsdelivr.net/gh/xiaose-code/picx-images-hosting@master/jianrong/image.1757q9h8ku.webp" loading="lazy" class="lazy"></p> <ul><li>外部接口：8个 IO 接口，5个使能信号（ALE、CLE、WE#、RE#、CE#），1个状态引脚（R/B#），1个写保护引脚（WP#）；</li> <li>命令、地址、数据都通过8个 IO 接口输入输出；</li> <li>写入命令、地址、数据时，都需要将 WE#、CE# 信号同时拉低，数据在 WE# 上升沿被锁存；</li> <li>CLE、ALE 用来区分 IO 引脚上传输的是数据还是地址。</li></ul> <p>从闪存控制器角度看，为了性能需求需要并发多个闪存 Die/LUN，通常配置有多个通道（channel）。一个通道挂多少个闪存 Die/LUN，取决于 SSD 容量和性能需求，Die/LUN 个数越多，并发的个数越多，性能越好。</p> <p>Die/LUN是闪存通信的最小基本管理单元，配有上述的一套总线，即8个I/O口，5个使能信号（ALE、CLE、WE#、RE#、CE#），1个状态引脚（R/B#），1个写保护引脚（WP#）……</p> <p>如果一个通道上挂了多个闪存 Die/LUN，每个 Die 共用每个通道上的一套总线，那闪存控制器如何识别和哪个 Die 通信呢？答案是通过选通信号 CE# 实现。在闪存控制器给特定地址的闪存 Die 发读写命令和数据前，先选通对应 Die 的 CE#信号，然后进行读写命令和数据的发送。一个通道上可以有多个 CE，SSD 主控一般设计为4～8个，对于容量而言选择有一定的灵活度。</p> <h2 id="_2-2-全闪存阵列-afa"><a href="#_2-2-全闪存阵列-afa" class="header-anchor">#</a> 2.2 全闪存阵列 AFA</h2> <p>U 盘是一两个闪存芯片和控制器封装，SSD 是很多 U 盘的阵列，全闪存阵列是很多 SSD 的阵列，只不过 U 盘是最差的闪存，SSD 好一点，AFA 用得更好。</p></div></div> <!----> <div class="page-edit"><!----> <!----> <div class="last-updated"><span class="prefix">上次更新:</span> <span class="time">2024/6/3 14:54:44</span></div></div> <div class="page-nav-wapper"><div class="page-nav-centre-wrap"><a href="/pages/4c6bf3/" class="page-nav-centre page-nav-centre-prev"><div class="tooltip">第1章 SSD综述</div></a> <a href="/pages/4f49cc/" class="page-nav-centre page-nav-centre-next"><div class="tooltip">第3章 SSD存储介质：闪存</div></a></div> <div class="page-nav"><p class="inner"><span class="prev">
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